1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device that operates in synchronization with a clock signal.
2. Description of the Background Art
FIG. 15 is a block diagram representing an arrangement of a portion related to read/write control of data of a conventional synchronous dynamic random access memory (hereinafter referred to as an SDRAM. In FIG. 15, the SDRAM includes input buffers 50 to 54, an output buffer 55, latch circuits 56 to 60, a command decoder 61, a row-related control signal generating circuit 62, a column-related control signal generating circuit 63, shift registers 64, 65, and an output-related control signal generating circuit 66.
Input buffer 50 generates an internal clock signal intCK according to an external clock signal CLK. Internal clock signal intCK is supplied to latch circuits 56 to 60, shift registers 64, 65, and column-related control signal generating circuit 63.
Input buffers 51 to 53 respectively transmit external control signals /RAS, /CAS, /WE to latch circuits 56 to 58. Latch circuits 56 to 58 respectively latch external control signals /RAS, /CAS, /WE, respectively generate internal control signals intR, intC, intW, and supply the generated signals to command decoder 61 in response to a rising edge of internal clock signal intCK.
Input buffer 54 and latch circuit 59 latch an external data signal DI and generate an internal data signal DIxe2x80x2 in response to a rising edge of internal clock signal intCK. Internal data signal DIxe2x80x2 is written into a memory cell selected via a data bus.
An internal data signal DOxe2x80x2 read from a selected memory cell is supplied to latch circuit 60 via a data bus. Latch circuit 60 and output buffer 55 latch internal data signal DOxe2x80x2 and generate an external data signal DO in response to a rising edge of internal clock signal intCK. When a signal OEM attains the logic high or the xe2x80x9cHxe2x80x9d level, data signal DO is output to the outside.
Command decoder 61 generates a row-related activating signal ACT and a column-related activating signals READ, WRITE according to a combination of logic levels of internal control signals intR, intC, intW. Row-related control signal generating circuit 62 generates a row address latch signal RAL, a word line trigger signal xcfx86WL, a bit line equalize signal BLEQ, a bit line interrupt signal BLI, a sense amplifier activating signal SE and the like according to signals ACT, READ, WRITE, and thus controls a row-related operation.
Shift register 64 takes in a level of signal ACT in response to each rising edge of internal clock signal intCK, and outputs the taken-in level of signal ACT in response to a succeeding rising edge of internal clock signal intCK. An output signal CDE of shift register 64 is supplied to column-related control signal generating circuit 63 and shift register 65.
Column-related control signal generating circuit 63 generates a column address latch signal CAL, a data input latch signal DIL, a column select line activating signal xcfx86CSL, an IO switching signal IOSW, an IO equalize signal IOEQ, a preamplifier activating signal PAE, a write driver activating signal WDE and the like according to signals CDE, READ, WRITE, intCK, and thus controls a column-related operation.
Shift register 65 takes in a level of signal CDE in response to each rising edge of internal clock signal intCK, and outputs the taken-in level of signal CDE in response to a succeeding rising edge of internal clock signal intCK. An output signal DBE of shift register 65 is supplied to output-related control signal generating circuit 66. Output-related control signal generating circuit 66 generates signal OEM according to signals DBE, READ. Signal OEM is supplied to output buffer 55.
FIG. 16 is a timing chart showing read control of an SDRAM in a case where a period TCLK of clock signal CLK is relatively short.
In FIG. 16, when an active command (/RAL=L, /CAS=H, /WE=H) is input in synchronization with a rising edge (time t0) of clock signal CLK (that is, intCK), internal control signals intR, intC, intW respectively attain the xe2x80x9cHxe2x80x9d level, the logic low or the xe2x80x9cLxe2x80x9d level, and the xe2x80x9cLxe2x80x9d level, and accordingly, signal ACT rises to the xe2x80x9cHxe2x80x9d level. When signal ACT rises to the xe2x80x9cHxe2x80x9d level, word line trigger signal xcfx86WL rises to the xe2x80x9cHxe2x80x9d level, and a selected word line WL rises to the xe2x80x9cHxe2x80x9d level. In addition, signal CDE rises to the xe2x80x9cHxe2x80x9d level in response to the second rising edge of clock signal CLK after signal ACT rises to the xe2x80x9cHxe2x80x9d level.
When a read command (/RAS=H, /CAS=L, /WE=H) is input in synchronization with the rising edge (time t2) of clock signal CLK that comes two clock cycles after the input of the active command, internal control signals intR, intC, intW, respectively attain the xe2x80x9cLxe2x80x9d level, the xe2x80x9cHxe2x80x9d level, and the xe2x80x9cLxe2x80x9d level, and accordingly, signal READ rises to the xe2x80x9cHxe2x80x9d level.
When signals CDE and READ both rise to the xe2x80x9cHxe2x80x9d level, column select line activating signal xcfx86CSL is raised to the xe2x80x9cHxe2x80x9d level, and a selected column select line CSL rises to the xe2x80x9cHxe2x80x9d level. In addition, signal DBE rises to the xe2x80x9cHxe2x80x9d level in response to the second rising edge (time t4) of clock signal CLK after signal CDE rises to the xe2x80x9cHxe2x80x9d level and read data signal DO is output to the outside.
In this manner, in a conventional SDRAM, a row-related read operation is performed in response to the input of an active command, and a read command is input after a prescribed clock cycle duration tRCD (the duration of two clock cycles in the chart) since the input of the active command. When the read command is input, a column-related read operation is performed, and read data signal DO is output to the outside after a prescribed clock cycle duration CL (a duration of two clock cycles in the chart) since the input of the read command.
The row-related read operation, however, terminates after a certain period of time since the input of the active command according to the performance of the SDRAM, and this time period does not necessarily equal an integer multiple of the period of clock signal CLK. Thus, as shown in FIG. 17, when a clock signal CLK having a relatively long period is used as in the system that requires numerous SDRAM to operate with stability, an RAS-CAS delay time tRCD becomes significantly longer than the time required for the row-related read operation so that there was a problem of a long wasteful standby time. The same was true of the data write operation.
Thus, the main object of the present invention is to provide a semiconductor memory device capable of read/write operation at a higher speed.
A semiconductor memory device according to the present invention is provided with an input circuit for taking in a plurality of external control signals in response to a clock signal changing from a first level to a second level, a decoder for selectively causing a first internal control signal or a second internal control signal to attain an active level according to the plurality of external control signals taken into the input circuit, a signal generating circuit for causing a third internal control signal to attain an active level in response to a predetermined time period having elapsed since the first internal control signal attained the active level and in response to the level of the clock signal changing, and a read/write circuit for performing part of data read/write operation in response to the first internal control signal attaining the active level and for performing the rest of data read/write operation in response to the second and third internal control signals both attaining the active level. Thus, even when the period of the clock signal is long, part of the data read/write operation is first started, and then after 1.5 clock cycles, the rest of the data read/write operation can be started so that the wasteful standby period can be shortened, and a higher speed read/write operation can be achieved.
Preferably, the signal generating circuit includes a delay circuit for delaying the first internal control signal for a predetermined time period, a pulse generating circuit for outputting a pulse signal every time the level of the clock signal changes, and a latch circuit for latching an output signal from the delay circuit in response to each pulse signal, and an output signal from the latch circuit becomes the third internal control signal. In this case, the signal generating circuit can be configured with ease.
In addition, another semiconductor memory device according to the present invention is provided with an input circuit for taking in a plurality of external control signals in response to a clock signal changing from a first level to a second level, a decoder for selectively causing a first internal control signal or a second internal control signal to attain an active level according to the plurality of external control signals taken into the input circuit, a signal generating circuit for causing a third internal control signal to attain an active level in response to the clock signal changing from the second level to the first level after the second internal control signal attains the active level, and a read/write circuit for performing part of data read/write operation in response to the first internal control signal attaining the active level, and for performing the rest of the data read/write operation in response to the second and third internal control signals both attaining the active level. Thus, even when the period of the clock signal is long, part of the data read/write operation is first started, and then after 1.5 clock cycles, the rest of the data read/write operation can be started so that the wasteful standby time can be shortened, and a higher speed read/write operation can be achieved.
Preferably, the signal generating circuit includes an inverter for receiving a clock signal and outputting an inverted clock signal, and a latch circuit for latching the second internal control signal in response to the inverted clock signal changing from a first level to a second level, and an output signal from the latch circuit becomes the third internal control signal. In this case, the signal generating circuit can be configured with ease.
In addition, a further semiconductor memory device according to the present invention is provided with an input circuit for taking in a plurality of external control signals in response to a clock signal changing from a first level to a second level, a decoder for selectively causing a first internal control signal or a second internal control signal to attain an active level according to the plurality of external control signals taken into the input circuit, a signal generating circuit for causing a third internal control signal to attain an active level in response to the clock signal having changed from the second level to the first level a predetermined number of times after the first internal control signal attained the active level, and a read/write circuit for performing part of data read/write operation in response to the first internal control signal attaining the active level, and for performing the rest of the data read/write operation in response to the second and third internal control signals both attaining the active level. Thus, even when the period of the clock signal is long, part of the data read/write operation is first started, and then after 1.5 clock cycles, the rest of the data read/write operation can be started so that the wasteful standby time can be shortened and a higher speed read/write operation can be achieved.
Preferably, the signal generating circuit includes an inverter for receiving a clock signal and outputting an inverted clock signal, and a shift register for taking in a level of the first internal control signal and outputting the level of the first internal control signal previously taken in, every time the inverted clock signal changes from the first level to the second level, and an output signal from the shift register becomes the third internal control signal. In this case, the signal generating circuit can be configured with ease.
More preferably, the above further semiconductor memory device according to the present invention is further provided with a setting circuit for selectively setting a fourth internal control signal to an active level or to an inactive level from outside, and the signal generating circuit causes the third internal control signal to attain the active level in response to the clock signal having changed from the second level to the first level a predetermined number of times when the fourth internal control signal is at the active level, and causes the third internal control signal to attain the active level in response to the clock signal having changed from the first level to the second level a predetermined number of times when the fourth internal control signal is at the inactive level. In this case, it can be selected at will whether to perform the rest of the read/write operation in response to a rising edge of the clock signal or in response to a falling edge of the clock signal.
More preferably, the signal generating circuit includes an inverter for receiving a clock signal and outputting an inverted clock signal, a gate circuit for receiving the clock signal and the inverted clock signal and for allowing the inverted clock signal to pass through when the fourth internal control signal is at the active level, while allowing the clock signal to pass through when the fourth internal control signal is at the inactive level, and a shift register for taking in a level of the first internal control signal and outputting the level of the first internal control signal previously taken in, every time the inverted clock signal or the clock signal that passes through the gate circuit changes from the first level to the second level, and an output signal from the shift register becomes the third internal control signal. In this case, the signal generating circuit can be configured with ease.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.